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ace24ac02 a3 two - wire serial eeprom ver 1. 3 1 description the ace24ac02a 3 is 2048 bits of serial electrical erasable and programmable read only memory, commonly known as eeprom. they are organized as 256 words of 8 bits (1 byte) each. the devices are fabricated with proprietary advanced cmos process for low power and low voltage applications. these devices are available in standard 8 - lead dip, 8 - lead sop, 8 - lead msop, 8 - lead tssop, 8 - lead dfn and sot - 23 - 5 packages. a standard 2 - wire serial interface is used to address all read and write functions. our extended vcc range (1.8v to 5.5v) devices enables wide spectrum of applications. features ? low voltage and low power operations: ace24 ac02a3 : vcc = 1.8v to 5.5v, industrial temperature range ( - 40 to 85 ). ace24 ac02a3 : with 3 bits device address, the devi ces are suitable for all application. (for use of 5 pins package, the device address a2 , a1, and a0 bits must be set to zero) ? maximum standby current < 1a ? 16 bytes page write mode. ? partial page write operation allowed. ? internally organized: 256 8 (2k). ? standard 2 - wire bi - directional serial interface. ? schmitt trigger, filtered inputs for noise protection. ? self - timed programming cycle (5ms maximum). ? 1 mhz (5v), 400 khz (1.8v, 2.5v, 2.7v) compatibility. ? automatic erase before write operation. ? write protect pin for hardware data protection. ? high reliability: typically 1,000,000 cycles endurance. ? 100 years data retention. ? standard 8 - pin dip/sop/msop/tssop/ t dfn and sot - 23 - 5 pb - free packages. absolute maximum ratings industrial operating temperature - 40 to 85 storage temperature - 50 to 125 input voltage on any pin relative to ground - 0.3v to v cc + 0.3v maximum voltage 8v esd protection on all pins >2000v *n otice : stresses exceed those listed under absolute maximum rating may cause permanent damage to the device. functional operation of the device at conditions beyond those listed in the specification is not guaranteed. prolonged exposure to extre me conditions may affect device reliability or functionality.
ace24ac02 a3 two - wire serial eeprom ver 1. 3 2 packaging type so p - 8 ts sop - 8 msop - 8 dip - 8 tdfn - 8 sot - 23 - 5 pin configurations ordering information ace24ac02a3 xx + x h pin name function a2,a1,a0 device address inputs sda serial data input / open drain output scl serial clock input wp write protect vcc powe r supply gnd ground nc no - connect pb - free u tube t tape and reel fm sop - 8 tm tssop - 8 om msop - 8 dp dip - 8 dm tdfn - 8 bn sot - 23 - 5 halogen - free
ace24ac02 a3 two - wire serial eeprom ver 1. 3 3 block diagram pin description a. s erial c lock (scl) the rising edge of this scl input is to latch data into the eeprom d evice while the falling edge of this clock is to clock data out of the eeprom device. b. s erial d ata l ine (sda) sda data line is a bi - directional signal for the serial devices. it is an open drain output signal and can be wired - or with other open - drain output devices. c. write protect(wp) the ace24ac02a3 devices have a wp pin to protect the whole eeprom array from programming. programming operations are allowed if wp pin is left un - connected or input to v il . conversely all programming functions are disabled if wp pin is connected to v ih or v cc . read operations is not affected by the wp pins input level. memory organization the ace24ac02a3 devices have 16 pages. since each page has 16 bytes, random word addressing to ace24ac02a3 will require 8 bits data word addr esses.
ace24ac02 a3 two - wire serial eeprom ver 1. 3 4 device operation a. s erial c lock a nd d ata t ransitions the sda pin is typically pulled to high by an external resistor. data is allowed to change only when serial clock scl is at vil. any sda signal transition may interpret as either a start or stop con dition as described below. b. start c onditions with scl v ih , a sda transition from high to low is interpreted as a start condition. all valid commands must begin with a start condition. c. s top c ondition with scl v ih , a sda transition from low to high is interpreted as a stop condition. all valid read or write commands end with a stop condition. the device goes into the standby mode if it is after a read command. a stop condition after page or byte write command will trigger the chip into the standby mode after the self - timed internal programming finis h. d. acknowledge the 2 - wire protocol transmits address and data to and from the eeprom in 8 bit words. the eeprom a cknowledge the data or address by outputting a "0" after receiving each word. the a cknowledge signal occurs on the 9th serial clock after each word. e. s tandby m ode the eeprom goes into low power standby mode after a fresh power up, after receiving a stop bit in read mode, or after completing a self - time internal programming operation. figure 3 : timing diagram for start and stop conditions figure 4 : timing diagram for output a cknowledge
ace24ac02 a3 two - wire serial eeprom ver 1. 3 5 device addressing the 2 - wire serial bus protocol mandates an 8 bits device address word after a start bit condition to invoke valid read or write command. the first four most significant bits of th e device address must be 1010, which is common to all serial eeprom devices. the next three bits are device address bits. these three device address bits (5 th , 6 th and 7 th ) are not cared and could be coded from 000 (b) to 111 (b). only one ace24ac02a3 devi ce can be used on the on 2 - wire bus. if a match is made, the eeprom device outputs an a cknowledge signal after the 8 th read/write bit, otherwise the chip will go into standby mode. the last or 8th bit is a read/write command bit. if the 8th bit is at vih t hen the chip goes into read mode. if a 0 is detected, the device enters programming mode. write operation s a. b yte w rite a byte write operation start s when a micro - controller sends a start bit condition, follows by a proper eeprom device address and then a write command. if the device address bits match the chip select address, the eeprom device will acknowledge at the 9 th clock cycle. the micro - controller will then send the rest of the lower 8 bits word address. at the 18 th cycle, the eeprom will acknowled ge the 8 - bit address word. the micro - controller will then transmit the 8 bit data. following an a cknowledge signal from the eeprom at the 27 th clock cycle, the micro - controller will issue a stop bit. after receiving the stop bit, the eeprom will go into a self - timed programming mode during which all external inputs will be disabled. after a programming time of t wc , the byte programming will finish and the eeprom device will return to the standby mode. b. p age w rite a page write is similar to a byte write with the exception that one to sixteen bytes can be programmed along the same page or memory row. all ace24ac02a3 are organized to have 16 bytes per memory row or page. with the same write command as the byte write, the micro - controller does not issue a stop bi t after sending the 1 st byte data and receiving the a cknowledge signal from the eeprom on the 27 th clock cycle. instead it sends out a second 8 - bit data word, with the eeprom acknowledging at the 36 th cycle. this data sending and eeprom acknowledging cycle repeats until the micro - controller sends a stop bit after the n 9 th clock cycle. after which the eeprom device will go into a self - timed partial or full page programming mode. after the page programming completes after a time of t wc , the devices will r eturn to the standby mode. the least significant 4 bits of the word address (column address) increments internally by one after receiving each data word. the rest of the word address bits (row address) do not change internally, but pointing to a specific memory row or page to be programmed. the first page write data word can be of any column address. up to 16 data words can be loaded into a page. if more then 16 data
ace24ac02 a3 two - wire serial eeprom ver 1. 3 6 words are loaded, the 17 th data word will be loaded to the 1 st data word column address. the 18 th data word will be loaded to the 2 nd data word column address and so on. in other word, data word address (column address) will roll over the previously loaded data. c. acknowledge p olling acknowledge polling may be used to poll the programming sta tus during a self - timed internal programming. by issuing a valid read or write address command, the eeprom will not acknowledge at the 9 th clock cycle if the device is still in the self - timed programming mode. however, if the programming completes and the chip has returned to the standby mode, the device will return a valid a cknowledge signal at the 9 th clock cycle. r ead o perations the read command is similar to the write command except the 8 th read/write bit in address word is set to 1. the three read o peration modes are described as follows: (a) c urrent a ddress r ead the eeprom internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. to initiate a current address read operation, t he micro - controller issues a start bit and a valid device address word with the read/write bit (8 th ) set to 1. the eeprom will response with an a cknowledge signal on the 9 t h serial clock cycle. an 8 - bit data word will then be serially clocked out. the in ternal address word counter will then automatically increase by one. for current address read the micro - controller will not issue an a cknowledge signal on the 18 th clock cycle. the micro - controller issues a valid stop bit after the 18 th clock cycle to ter minate the read operation. the device then returns to standby mode. (b) s equential r ead the sequential read is very similar to current address read. the micro - controller issues a start bit and a valid device address word with read/write bit (8 th ) set to 1. t he eeprom will response with an a cknowledge signal on the 9 th serial clock cycle. an 8 - bit data word will then be serially clocked out. meanwhile the internally address word counter will then automatically increase by one. unlike current address read, the micro - controller sends an a cknowledge signal on the 18 th clock cycle signaling the eeprom device that it wants another byte of data. upon receiving the a cknowledge signal, the eeprom will serially clocked out an 8 - bit data word based on the incremented in ternal address counter. if the micro - controller needs another data, it sends out an a cknowledge signal on the 27 th clock cycle. another 8 - bit data word will then be serially clocked out. this sequential read continues as long as the micro - controller sends an a cknowledge signal after receiving a new data word. when the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. similar to current ad dress read, the micro - controller can terminate the sequential read by not acknowledging the last data word received, but sending a stop bit afterwards instead.
ace24ac02 a3 two - wire serial eeprom ver 1. 3 7 (c) r andom r ead random read is a two - steps process. the first step is to initialize the internal address counter with a target read address usin g a du mmy write instruction. the second step is a current address read. to initialize the internal address counter with a target read address, the micro - controller issues a start bit first, follows by a valid device address with the read/write bit (8 th ) set to 0. the eeprom will then acknowledge . the micro - controller wi ll then send the address word. again the eeprom will acknowledge . instead of sending a valid written data to the eeprom, the micro - controller performs a current address read instruction to read the data. note t hat once a start bit is issued, the eeprom will reset the internal programming process and continue to execute the new instruction which is to read the current address. figure 5 : byte write figure 6 : page write figure 7 : current address read
ace24ac02 a3 two - wire serial eeprom ver 1. 3 8 figure 8 : sequential read figure 9 : random read figure 10 : scl and sda bus timing
ace24ac02 a3 two - wire serial eeprom ver 1. 3 9 ac characteristics symbol parameter 1.8v - 2.7v 5.0v units min max min max f scl clock frequency, scl 400 1000 khz t low clock pulse width low 1.3 0.4 s t high clock pulse width high 0.6 0.4 s t i noise suppression time (1) 180 120 ns t aa clock low to data out valid 0.3 0.9 0.2 0.55 s t buf time the bus must be free before a new transmission can start 1.3 0.5 s t hd.sta start hold time 0.6 0.25 s t su.sta start set - up time 0.6 0.25 s t hd.dat data in hold time 0 0 s t su.dat data in set - up time 100 100 ns t r inputs rise time 0.3 0.3 s t f inputs fall time 300 100 n s t su.sto st op setup time 0.6 0.25 s t dh data out hold time 50 50 ns t wr write cycle time 5 5 ms endurance (1) 25 , page mode , 3.3 v 1,000,000 write cycles notes* 1. t his parameter is expected by characterization but is not fully screened by test. 2. ac measurement conditions: r l (connects to vcc): 1.3k input pulse voltages: 0.3vcc to 0.7vcc input and output timing ref erence voltages: 0.5vcc
ace24ac02 a3 two - wire serial eeprom ver 1. 3 10 dc characteristics symbol parameter test condition min typ max unit s v cc 1 power supply vcc 1.8 5.5 v i cc supply current v cc @ 5 . 0 v, read = 400 khz 0.5 1.0 ma i cc supply current v cc @ 5 . 0 v, write = 400 khz 2.0 3.0 ma i sb1 standby current v cc @ 1.8 v, v in = v cc or v ss 1.0 a i sb2 standby current v cc @ 2. 5 v, v in = v cc or v ss 1.0 a i sb 3 standby current v cc @5. 0 v, v in = v cc or v ss 0.07 1.0 i li input leakage current v in = v cc or v ss 3.0 a i lo output leakage curren t v in = v cc or v ss 3.0 a v il input low level - 0.6 v cc * 0.3 v v ih input high level v cc * 0.7 v cc + 0. 5 v v ol 1 output low level v cc @ 1 .8 v, i ol = 0.15 ma 0.2 v v ol 2 output low level v cc @3.0 v, i ol = 2.1 ma 0.4 v
ace24ac02 a3 two - wire serial eeprom ver 1. 3 11 packaging informa tion dip - 8 symbol dimensions in millimeters dimensions in inches min max min max a 3.710 4.310 0.146 0.170 a1 0.510 0.020 a2 3.200 3.600 0.126 0.142 b 0.380 0.570 0.015 0.022 b1 1.524 bsc 0.060 bsc c 0.204 0.360 0.008 0.014 d 9.000 9.400 0.354 0.370 e 6.200 6.600 0.244 0.260 e1 7.320 7.920 0.288 0.312 e 2.540 (bsc) 0.100 bsc l 3.000 3.600 0.118 0.142 e2 8.400 9.000 0.331 0.354
ace24ac02 a3 two - wire serial eeprom ver 1. 3 12 packaging information tssop - 8 symbol dimensions in millimeters dimensions in inches min max min max d 2.900 3.100 0.114 0.122 e 4.300 4.500 0.169 0.177 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 e1 6.250 6.550 0.246 0.258 a 1.100 0.043 a2 0.800 1.000 0.031 0.039 a1 0.020 0.150 0.001 0.006 e 0.65 (bsc) 0.026 (bsc) l 0.500 0.700 0.020 0.028 h 0.25 (typ) 0.01 (typ) 1 7 1 7
ace24ac02 a3 two - wire serial eeprom ver 1. 3 13 packaging information sop - 8 symbol dimensions in millimeters dimensions in inches min max min max a 1.350 1.750 0.053 0.069 a1 0.100 0.250 0.004 0.010 a2 1.350 1.550 0.053 0.061 b 0.330 0 .510 0.013 0.020 c 0.170 0.250 0.006 0.010 d 4.700 5.100 0.185 0.200 e 3.800 4.000 0.150 0.157 e1 5.800 6.200 0.228 0.244 e 1.270 (bsc) 0.050 (bsc) l 0.400 1.270 0.016 0.050 0 8 0 8
ace24ac02 a3 two - wire serial eeprom ver 1. 3 14 packaging information msop - 8 symbol dimensions in mi llimeters dimensions in inches min max min max a 0.820 1.100 0.320 0.043 a1 0.020 0.150 0.001 0.006 a2 0.750 0.950 0.030 0.037 b 0.250 0.380 0.010 0.015 c 0.090 0.230 0.004 0.009 d 2.900 3.100 0.114 0.122 e 0.65 (bsc) 0.026 (bsc) e 2.900 3.100 0. 114 0.122 e1 4.750 5.050 0.187 0.199 l 0.400 0.800 0.016 0.031 0 6 0 6
ace24ac02 a3 two - wire serial eeprom ver 1. 3 15 packaging information tdfn - 8 symbol dimensions in millimeters min nom max a 0.70 0.75 0.80 a1 - 0.02 0.05 b 0.18 0.25 0.30 c 0.18 0.20 0.25 d 1.90 2.00 2.10 d2 1.50ref e 0.50bsc nd 1.50bsc e 2 .90 3.00 3.10 e2 1.60ref l 0.30 0.40 0.50 h 0.20 0.25 0.30 l/f surface electroplate nipdau (nickel, pd, metal) dimension mil 67*75
ace24ac02 a3 two - wire serial eeprom ver 1. 3 16 packaging information sot23 - 5 symbol dimensions in millimeters dimensio ns in inches min max min max a 1.050 1.250 0.041 0.049 a1 0.000 0.100 0.000 0.004 a2 1.050 1.150 0.041 0.045 b 0.300 0.500 0.012 0.020 c 0.100 0.200 0.004 0.008 d 2.820 3.020 0.111 0.119 e 1.500 1.700 0.059 0.067 e1 2.650 2.950 0.104 0.116 e 0.9 5 (bsc) 0.037 (bsc) e1 1.800 2.000 0.071 0.079 l 0.300 0.600 0.012 0.024 0 8 0 6
ace24ac02 a3 two - wire serial eeprom ver 1. 3 17 notes ace does not assume any responsibility for use as critical components in life support devices or systems withou t the express written approval of the president and general counsel of ace electronics co., ltd. as sued herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain li fe, and shoes failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device o r system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ace technology co., ltd. http://www.ace - ele.com/

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